The present invention relates generally to semiconductor fabrication and more specifically to fabricating STIs (shallow trench isolation structures).
The current deep shallow trench isolation (STI) methods are difficult.
U.S. Pat. No. 5,700,712 to Schwalke et al. describes a method for producing an insulating trench in a silicon-on-insulator (SOI) substrate having integrated logic elements and high-voltage power components. A trench extending down to an insulating layer is etched and covered with a doped silicon structure. Diffusion regions proximate the trench are formed by drive-out from the doped amorphous silicon structure and an insulation structure is simultaneously produced in the trench by oxidation of the doped silicon structure.
U.S. Pat. No. 5,387,538 to Moslehi describes a method for forming semiconductor device isolation structure.
U.S. Pat. No. 4,471,525 to Sasaki describes a method for manufacturing a semiconductor device utilizing a two-step etch and selective oxidation to form isolation regions.
U.S. Pat. No. 4,942,137 to Sivan et al. describes a method for fabricating a self-aligned trench structure in a semiconductor device.
U.S. Pat. No. 5,930,646 to Gerung et al. describes a process for forming isolations of uniform thickness in narrow and wide trenches.
U.S. Pat. No. 4,847,214 to Robb et al. describes a method for filling trenches from a seed layer.
U.S. Pat. No. 4,256,514 to Pogge describes a method for forming a narrow dimensioned, e.g. submicron, region on a silicon body.
U.S. Pat. No. 4,528,047 to Beyer et al. describes a method for forming a void free isolation structure utilizing etch and fill techniques.
Accordingly, it is an object of the present invention to provide an improved method of forming a deep shallow trench isolation structure.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.